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Home ยป Mlcached: Multi-level DRAM-NAND Key-value Cache
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Mlcached: Multi-level DRAM-NAND Key-value Cache

Authors: 

I. Stephen Choi, Byoung Young Ahn, and Yang-Suk Kee, Samsung Memory Solutions Lab

Abstract: 

We present Mlcached, multi-level DRAM-NAND keyvalue cache, that is designed to enable independent resource provisioning of DRAM and NAND flash memory by completely decoupling each caching layers. Mlcached utilizes DRAM for L1 cache and our new KVcache device for L2 cache. The index-integrated FTL is implemented in the KV-cache device to eliminate any inmemory indexes that prohibit the independent resource provisioning. We show that Mlcached is only 12.8% slower than a DRAM-only Web caching service in the average RTT with 80% L1 cache hit while saving twothirds of its TCO. Moreover, our model-based study shows that Mlcached can provide up to 6X lower cost or 4X lower latency at the same SLA or TCO, respectively.

I. Stephen Choi, Samsung Memory Solutions Lab

Byoung Young Ahn, Samsung Memory Solutions Lab

Yang-Suk Kee, Samsung Memory Solutions Lab

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BibTeX
@inproceedings {196330,
author = {I. Stephen Choi and Byoung Young Ahn and Yang-Suk Kee},
title = {Mlcached: Multi-level {DRAM-NAND} Key-value Cache},
booktitle = {8th USENIX Workshop on Hot Topics in Cloud Computing (HotCloud 16)},
year = {2016},
address = {Denver, CO},
url = {https://www.usenix.org/conference/hotcloud16/workshop-program/presentation/choi},
publisher = {USENIX Association},
month = jun,
}
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