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Elastic Scaling for Transactional Memory: From Centralized to Distributed Architectures
D. Didona, Instituto Superior Técnico/INESC-ID, Portugal; P. Felber and D. Harmanci, University of Neuchâtel, Switzerland; P. Romano, Instituto Superior Técnico/INESC-ID, Portugal; J. Schenker, University of Neuchâtel, Switzerland
In this paper we investigate the issue of automatically identifying the "natural" degree of parallelism of an application, i.e., the workload-specific threshold below which increasing concurrency will improve transactions throughput and over which addition concurrency will not help and might even degrade performance because of higher contention and abort rates, even if sufficient physical resources are available. Throughout this paper, we discuss the importance of adapting the concurrency level to the workload in various application settings. We provide empirical evidence of this, taken from two extreme scenarios: a shared-memory system with a low-level STM library written in C, and a distributed system with a high-level DSTM infrastructure written in Java. We overview two alternative self-tuning methodologies, based on on-line exploration and on model-driven performance forecasting techniques, and discuss how both approaches can be combined in order to maximize robustness and convergence speed towards optimum solutions.
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