microSCALE: Static Analysis for Microarchitectural Side-channel Leakage Evaluation

Developing cryptographic implementations that are resistant to side-channel attacks is challenging in modern CPUs. Data-dependent switching activity induces subtle transitions deep in the microarchitecture that can cause sensitive information to leak through the CPU's power consumption. Existing leakage detection tools largely rely on simulation-based testing, which is not only time-consuming but is also limited to the explored execution scenarios.

We present microSCALE, a fully automated framework for detecting power side-channel leakages that occur due to transitions in the CPU's microarchitecture. By statically analyzing the CPU's RTL, microSCALE enables systematic exploration of microarchitectural leakage sources within seconds. It precisely localizes the origin of leakage in the hardware and traces it back to the corresponding software instructions. We evaluate microSCALE on several protected crypto-implementations, including GIFT, ASCON, PRESENT, and AES, running on an open-source RISC-V processor, and identify several leakage sources. For instance, we identify that a protected implementation of the GIFT cipher has about 80% of its instructions that leak on the Rocket Core. We show how microSCALE can help in hardening this implementation, reducing the side-channel leakage around 90.3%.