BIBIM: A Prototype Multi-Partition Aware Heterogeneous New Memory

We describe a prototype multi-partition aware new memory controller and subsystem that precisely integrates DRAM with 3x nm phase change RAM (PRAM), referred to as BIBIM. In this work, we reveal main challenges of a new type of PRAMs in getting closer to main processors by evaluating our real 3x nm PRAM with persistent memory benchmarks. BIBIM implements hybrid cache logic into a 2x nm FPGA device, which can hide long latency imposed by the underlying PRAM modules as well as support persistent operations. The cache logic of our controller can also serve multiple read requests while writing data into a target PRAM bank by taking into account PRAM’s multi-partition architecture. The evaluation results demonstrate that the read and write latency of our BIBIM is 115 ns and 125 ns, which are 38% and 99% better than a pure PRAM-based memory subsystem. In addition, BIBIM can remove blocking reads by 53%, on average, thereby shortening average write-after-read latency by 48%.