Couture: Tailoring STT-MRAM for Persistent Main Memory


Mustafa Shihab, The University of Texas at Dallas; Jie Zhang, Yonsei University; Shuwen Gao, Intel; Joseph Callenes–Sloan, The University of Texas at Dallas; Myoungsoo Jung, Yonsei University


Modern computer systems rely extensively on dynamic random-access memory (DRAM) to bridge the performance gap between on-chip cache and secondary storage. However, continuous process scaling has exposed DRAM to high off-state leakage and excessive power consumption from frequent refresh operations. Spintransfer torque magnetoresistive RAM (STT-MRAM) is a plausible replacement for DRAM, given its high endurance and near-zero leakage. However, conventional STT-MRAM cannot directly substitute DRAM due to its large cell space area and the high latency and energy costs for writes. In this work, we present Couture – a main memory design using tailored STT-MRAM that can offer a storage density comparable to DRAM and high performance with low-power consumption. In addition, we propose an intelligent data scrubbing method (iScrub) to ensure data integrity with minimum overhead. Our evaluation results show that, equipped with the iScrub policy, our proposed Couture can achieve up to 23% performance improvement, while consuming 18% less energy, on average, compared to a contemporary DRAM.

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@inproceedings {200118,
author = {Mustafa Shihab and Jie Zhang and Shuwen Gao and Josep Sloan and Myoungsoo Jung},
title = {Couture: Tailoring STT-MRAM for Persistent Main Memory},
booktitle = {4th Workshop on Interactions of NVM/Flash with Operating Systems and Workloads ({INFLOW} 16)},
year = {2016},
address = {Savannah, GA},
url = {},
publisher = {{USENIX} Association},