AlNiCo: SmartNIC-accelerated Contention-aware Request Scheduling for Transaction Processing


Junru Li, Youyou Lu, Qing Wang, Jiazhen Lin, Zhe Yang, and Jiwu Shu, Tsinghua University


High-performance transaction processing needs to schedule numerous requests from the network. However, such request scheduling comes with costs of complex information gathering and considerable computation. We observe that emerging SmartNICs pose opportunities for transaction scheduling with low overhead. In this paper, we propose AlNiCo, which leverages SmartNICs to intelligently schedule incoming transaction requests to CPU cores, minimizing inter-transaction contention with low latency. AlNiCo describes the contention according to system states in a way that SmartNICs can efficiently process, and co-designs hardware and software to enable flexible and adaptive scheduling. We implement AlNiCo using FPGA-equipped Innova-2 SmartNICs, and our evaluation shows that AlNiCo boosts the throughput by 1.30 times sim 2.68 times and reduces the latency by up to 48.8%.

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@inproceedings {280678,
author = {Junru Li and Youyou Lu and Qing Wang and Jiazhen Lin and Zhe Yang and Jiwu Shu},
title = {{AlNiCo}: {SmartNIC-accelerated} Contention-aware Request Scheduling for Transaction Processing},
booktitle = {2022 USENIX Annual Technical Conference (USENIX ATC 22)},
year = {2022},
isbn = {978-1-939133-29-8},
address = {Carlsbad, CA},
pages = {951--966},
url = {},
publisher = {USENIX Association},
month = jul

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