Workshop Program

We begin with an examination of the technical value propositions of flash memory in the data center from the perspective of the major workload types in the data tier. We survey recent work in exposing and exploiting flash memory technology’s key capabilities through software in the control and data planes, and roadmap the major integrations needed in order to deliver on the promised value propositions.

The conversation will then shift to creating blueprints for successful deployment of flash technology at scale. The blueprints are categorized by market segments and scale. They guide us in prioritizing OS research for supporting the most suitable attach points and form factors, interfaces and protocols, standards and open source, benchmarks and workloads.

The final remarks will address the exploration-convergence dilemma before us, forcing us to choose: between creative application and standardization; between device-level and service-level offerings; between flash as memory and flash as disk; and between control-plane and data-plane value propositions. It is argued that these are often false choices, that a "both…and" approach will prove superior to an "either…or" approach in order to justify the level of economic investment needed for realizing our vision of an all-flash data center.

Dr. Pankaj Mehra is currently SanDisk Senior Fellow. He was SVP & CTO at enterprise flash technology pioneer Fusion-io and before that at Whodini, an e-mail analytics company he founded. Appointed a Distinguished Technologist at Hewlett-Packard in 2004 for his groundbreaking work on persistent memory, Pankaj went on to found HP Labs Russia where he was Chief Scientist until 2010, and where he incubated Taxonom.com, a cloud service for creating ontologies from queries, document collections, and examples. He previously served on the faculty of IIT, Delhi and UC Santa Cruz. Pankaj’s 48 filed patents, 29 papers, and 3 books cover a range of topics in scalable intelligent systems, and his engineered systems have held TPC-C and Terabyte Sort performance records and won recognition from NASA and Sandia National Labs. Pankaj volunteers at MMDS Foundation as their industry liaison chair, and previously served on the editorial boards of IEEE Internet Computing and Transactions on Computers, and on numerous program committees ranging from SuperComputing to International Semantic Web Conference.

Janus is a system for partitioning the flash storage tier between workloads in a cloud-scale distributed file system with two tiers, flash storage and disk. The file system stores newly created files in the flash tier and moves them to the disk tier using either a First-In-First-Out (FIFO) policy or a Least-Recently-Used (LRU) policy, subject to per-workload allocations. Janus periodically computes the optimal partitioning of the available flash between workloads to maximize the total reads sent to the flash tier, based on the measured workload characteristics. This talk will describe the motivation behind the design of Janus, some of the analytical techniques used to model the workloads, the implementation, and some results.

Arif Merchant is a Research Scientist with the Storage Analytics group at Google, where he studies interactions between components of the storage stack. Prior to this, he was with HP Labs, where he worked on storage QoS, distributed storage systems, and stochastic models of storage. He holds the B.Tech. degree from IIT Bombay and the Ph.D. in Computer Science from Stanford University. He is an ACM Distinguished Scientist.

What makes one workload perform well on a particular SSD, and another poorly? How can we estimate performance from workload parameters? This talk will review recent results in analytic modeling of FTL performance and show how these results may be used not only to answer these questions, but to modify workloads and FTLs for better performance.

Peter Desnoyers is an associate professor at Northeastern University. He received his Ph.D. in Computer Science from the University of Massachusetts, Amherst in 2008. Prior to that he spent fifteen years as an engineer in storage and networking industries, at Apple, Motorola, and a number of start-ups, after receiving the BS and MS degrees in EECS from MIT in 1988. His research focuses on operating systems and storage, drawing on his experience to explore practical solutions to the problems of tomorrow's applications and devices.

Compression is widely used in storage systems to reduce the amount of data that is written to physical storage devices, in order to improve both bandwidth and price per GB. In SSDs, which use NAND flash devices, compression also helps to improve endurance, which is limited to a fixed number of raw bytes written to the media, and to reduce garbage-collection overheads.

Compression is typically implemented in one of three layers: the application, the file system or the firmware of the storage device. Our main findings are that compression embedded within the SSD outperforms the built-in host-side compression engines of a well-known database and file systems. Therefore we focus on intra-SSD compression schemes. We investigate the effects of compression granularity and the arrangement of compressed data in NAND flash pages on data reduction and the lifetime of the SSD. We compare several schemes in this design space, some taken from the literature and some new.

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29. Also, its implementation overhead is small, and it incurs very small performance and energy loss.