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USENIX Annual Technical Conference (NO 98), 1998
Abstract
Implementation of Multiple Pagesize Support in HP-UX
Indira Subramanian, Cliff Mather,
Kurt Peterson, and Balakrishna Raghunath
Hewlett-Packard Company
Abstract
To reduce performance degradation from Translation Lookaside Buffer (TLB) misses without significant increase in TLB size, most modern processors
implement TLBs that support multiple pagesizes. For
example, Hewlett-Packard's PA-8000 processor allows
8 hardware pagesizes, in multiples of four, ranging
from 4 Kbytes to 64 Mbytes.
In implementing multiple pagesize support in
HP-UX, we chose to create large pages at page-fault
service time. We have a buddy system allocator that
provides interfaces for allocating and freeing multiple
pagesizes. We maintain the Virtual Memory (VM)
data structures such as the pagetable entry, virtual
page frame descriptor, and physical page frame descriptor based on the smallest pagesize, and represent
a large pagesize as a collection of these base pagesize structures. In our implementation, VM operations on a large pagesize such as 16KB are carried out
by looping over the 4KB-based constituent VM data
structures. Our system offers signifiant application
performance improvement when using large pagesizes.
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