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The true cost of accurate time has so far often been ignored in the design of low-power embedded systems. The development of the STU will for the first time enable true low-power time synchronization protocols by exploiting the fact that we don't always need high precision, and can thus duty-cycle high frequency clocks. By adding a low-power FPGA to our design, we created a flexible platform that allows us to implement, and test new algorithms for timer units that could be included in future low-power microprocessors directly.

Figure 7: Power consumption of the Igloo AGL600V2 while duty-cycling the fast 48MHz clock.

Thomas Schmid 2008-11-14