Preliminary Results

Parallel to our prototype design, we also began to evaluate the effects of the combination of a fast (8 MHz) XCXT with a slow (32 KHz) oscillator. Intuitively, one could view the periodic re-calibration (shown in Figure 3) of the slow clock by the high accuracy XCXT as a two-staged duty cycled system itself. To analyze the overall power consumption of the STU, one would need to compute the duty cycle of this subsystem. Since the frequency of the slow clock drifts primarily due to changes in temperature, it would be natural to presume that the duty cycle and, in effect, the time interval between compensations depends on the change in the environmental temperature. Thus, any meaningful evaluation of STU performance requires to be done on real temperature data.

Figure 6 illustrates the result of a simulation setup of the STU using a 3 year temperature trace from a wildlife reserve in California. Though this setting does not represent the harshest of temperature variations, it emulates a reasonable set of outdoor conditions suitable for early evaluation. The top trace depicts the temperature variation and clearly shows seasonal changes (and less clearly, diurnal changes). The middle trace is an estimate of the re-compensation interval based on the rate of the change of temperature and the accuracy of the XCXT at that temperature. (The re-compensation attempts to maintain the stability of the slow clock to below 1 $ppm$.) This estimate is fairly optimisitic since it assumes knowledge of future temperature gradients. In an actual implementation, the XCXT would use its $\delta f_{12}$ sensing as a proxy to track changes in environmental temperature. Using measurements gleaned from development boards, a state model of the STU power consumption was constructed, utilizing which the bottom trace shows the average power consumption for this temperature trace.

Figure 6: In a simulation of 3 years of temperature data, the Smart Timer Unit achieves $<400\mu W$.

To show that duty-cycling fast clocks has a vast effect on the power consumption, we instantiated two counters on an Igloo FPGA. The first counter was connected to a low frequency oscillator, whereas the second one was connected to a 48 MHz clock. In regular intervals, based on the slow counter, we enabled and disabled the fast oscillator and measured the power consumption of the FPGA core. Figure 7 shows the result. We can clearly see that the average power consumption drops drastically while with the STU concept, a stable clock can still be achieved.