Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX

Authors: 

Craig Disselkoen, David Kohlbrenner, Leo Porter, and Dean Tullsen, University of California, San Diego

Abstract: 

Last-Level Cache (LLC) attacks typically exploit timing side channels in hardware, and thus rely heavily on timers for their operation. Many proposed defenses against such side-channel attacks capitalize on this reliance. This paper presents PRIME+ABORT, a new cache attack which bypasses these defenses by not depending on timers for its function. Instead of a timing side channel, PRIME+ABORT leverages the Intel TSX hardware widely available in both server- and consumer-grade processors. This work shows that PRIME+ABORT is not only invulnerable to important classes of defenses, it also outperforms state-of-the-art LLC PRIME+PROBE attacks in both accuracy and efficiency, having a maximum detection speed (in events per second) 3× higher than LLC PRIME+PROBE on Intel’s Skylake architecture while producing fewer false positives.

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BibTeX
@inproceedings {203658,
author = {Craig Disselkoen and David Kohlbrenner and Leo Porter and Dean Tullsen},
title = {Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel {TSX}},
booktitle = {26th {USENIX} Security Symposium ({USENIX} Security 17)},
year = {2017},
isbn = {978-1-931971-40-9},
address = {Vancouver, BC},
pages = {51--67},
url = {https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/disselkoen},
publisher = {{USENIX} Association},
}