Translation Pass-Through for Near-Native Paging Performance in VMs


Shai Bergman and Mark Silberstein, Technion; Takahiro Shinagawa, University of Tokyo; Peter Pietzuch and Lluís Vilanova, Imperial College London


Virtual machines~(VMs) are used for consolidation, isolation, and provisioning in the cloud, but applications with large working sets are impacted by the overheads of memory address translation in VMs. Existing translation approaches incur non-trivial overheads: (i)~nested paging has a worst-case latency that increases with page table depth; and (ii)~paravirtualized and shadow paging suffer from high hypervisor intervention costs when updating guest page tables.

We describe Translation Pass-Through (TPT), a new memory virtualization mechanism that achieves near-native performance. TPT enables VMs to control virtual memory translation from guest-virtual to host-physical addresses using one-dimensional page tables. At the same time, inter-VM isolation is enforced by the host by exploiting new hardware support for physical memory tagging in commodity CPUs.

We prototype TPT by modifying the KVM/QEMU hypervisor and enlightening the Linux guest. We evaluate it by emulating the memory tagging mechanism of AMD CPUs. Our conservative performance estimates show that TPT achieves native performance for real-world data center applications, with speedups of up to 2.4× and 1.4× over nested and shadow paging, respectively.

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@inproceedings {288762,
author = {Shai Bergman and Mark Silberstein and Takahiro Shinagawa and Peter Pietzuch and Llu{\'\i}s Vilanova},
title = {Translation {Pass-Through} for {Near-Native} Paging Performance in {VMs}},
booktitle = {2023 USENIX Annual Technical Conference (USENIX ATC 23)},
year = {2023},
isbn = {978-1-939133-35-9},
address = {Boston, MA},
pages = {753--768},
url = {},
publisher = {USENIX Association},
month = jul