Check out the new USENIX Web site.
... SIZE="-1">{cort,yodaiken}@cs.nmt.edu1
This work was partially funded by Sandia National Labs Grant 29P-9-TG100
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... modifications.3
On a SMP machine we might see conflicts due to accesses causing cache operations on other processors or, more likely, all these writes to memory using a great deal of the bus while the other processor needs it
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Cort Dougan
1999-01-04