4th USENIX Conference on File and Storage TechnologiesAbstract
Pp. 267280 of the Proceedings
A Scalable and High Performance Software iSCSI Implementation
Abhijeet Joglekar, Michael E. Kounavis, and Frank L. Berry, Intel Research and Development, Hillsboro, OR
In this paper we present two novel techniques for
improving the performance of the Internet Small Computer Systems Interface (iSCSI) protocol, which is
the basis for IP-based networked block storage today.
We demonstrate that by making a few modifications to
an existing iSCSI implementation, it is possible to
increase the iSCSI protocol processing throughput from
1.4 Gbps to 3.6 Gbps. Our solution scales with the CPU
clock speed and can be easily implemented in software
using any general purpose processor without requiring
specialized iSCSI protocol processing hardware.
To gain an in-depth understanding of the processing
costs associated with an iSCSI protocol
implementation, we built an iSCSI fast path in a userlevel
sandbox environment. We discovered that the
generation of Cyclic Redundancy Codes (CRCs) which
is required for data integrity, and the data copy
operations which are required for the interaction
between iSCSI and TCP represent the main bottlenecks
in iSCSI protocol processing. We propose two
optimizations to iSCSI implementations to address
these bottlenecks. Our first optimization is on the way
CRCs are being calculated. We replace the industry
standard algorithm proposed by Prof. Dilip Sarwate
with 'Slicing-by-8' (SB8), a new algorithm capable of
ideally reading arbitrarily large amounts of data at a
time while keeping its memory requirement at
reasonable level. Our second optimization is on the way
iSCSI interacts with the TCP layer. We interleave the
compute-intensive data integrity checks with the
memory access-intensive data copy operations to
benefit from cache effects and hardware pipeline
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