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USENIX Technical Program - Abstract - Domain-Specific Languages 99
Verischemelog: Verilog embedded in Scheme
James Jennings and Eric Beuscher, Tulane University
Abstract
Verischemelog (pronounced with 5 syllables, ver-uh-scheme-uh-log) is a
language and programming environment embedded in Scheme for designing
digital electronic hardware systems and for controlling the simulatin
of these circuits. Simulation is performed by a separate program,
often a commercial product. Verischemelog compiles to Verilog, an
industry standard language accepted by several commercial and public
domain simulators.
Because many design elements are easily
parameterized, design engineers currently write scripts which generate
hardware description code in Verilog. These scripts work by textual
substitution, and are typically ad-hoc and quite limited.
Preprocessors for Verilog, on the other hand, are hampered by their
macro-expansion languages, which support few data types and lack
procedures. Verischemelog obviates the need for scripts and
prepocessors by providing a hardware description language with
list-based syntax, and Scheme to manipulate it.
An interactive
development environment gives early and specific feedback about
errors, and structured access to the compiler and run-time environment
provide a high degree of reconfigurability and extensibility of
Verischemelog.
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